intelligent dynamic clock switch (idcs) pll clock driver mpc9993 rev 3, 06/2005 freescale semiconductor technical data ? freescale semiconductor, in c., 2005. all rights reserved. intelligent dynamic clock switch (idcs) pll clock driver the mpc9993 is a pll clock driver designed specifically for redundant clock tree designs. the device receives two differential lvpecl clock signals from which it generates 5 new differential lvpecl clock outputs. two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. features ? fully integrated pll ? intelligent dynamic clock switch ? lvpecl clock outputs ? lvcmos control i/o ? 3.3 v operation ? 32-lead lqfp packaging ? 32-lead pb-free package available functional description the mpc9993 intelligent dynamic clo ck switch (idcs) circuit continuously monitors both input clk signals. upon detec tion of a failure (clk stuck high or low for at least 1 period), the inp_bad fo r that clk will be latched (h). if that clk is the primary clock, the idcs will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. the typical phase bump caused by a fail ed clock is eliminated. (see application information section). fa suffix 32-lead lqfp package case 873a-04 ac suffix 32-lead lqfp package pb-free package case 873a-04 mpc9993 intelligent dynamic clock switch pll clock driver clk0 clk0 clk1 clk1 ext_fb ext_fb sel_clk dynamic switch logic pll pll_en 8 16 qb0 qb0 qb1 qb1 qb2 qb2 qa0 qa0 qa1 qa1 mr man_override clk_selected inp1bad inp0bad alarm_reset 800 ? 1600 mhz or figure 1. block diagram data sheet mpc9993 idt? intelligent dynamic clock switch (idcs) pll clock driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9993 1
idt? intelligent dynamic clock switch (idcs) pll clock driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9993 2 mpc9993 intelligent dynamic clock switch (idcs) pll clock driver netcom advanced clock drivers device data 2 freescale semiconductor mpc9993 figure 2. 32-lead pinout (top view) table 1. pin descriptions pin name i/o pin definition clk0, clk0 clk1, clk1 lvpecl input lvpecl input differential pll clock reference (clk0 pulldown, clk0 pullup) differential pll clock reference (clk1 pulldown, clk1 pullup) ext_fb, ext_fb lvpecl input differential pll feedback clock (ext_fb pulldown, ext_fb pullup) qa0:1, qa0:1 lvpecl output differential 1x output pairs qb0:2, qb0:2 lvpecl output differential 2x output pairs inp0bad lvcmos output indicates detection of a bad input reference clock 0 with respect to the feedback signal. the output is active high and will remain high until the alarm reset is asserted inp1bad lvcmos output indicates detection of a bad input reference clock 1 with respect to the feedback signal. the output is active high and will remain high until the alarm reset is asserted clk_selected lvcmos output ?0' if clock 0 is selected, ?1' if clock 1 is selected alarm_reset lvcmos input ?0' will reset the input bad flags and align clk_sele cted with sel_clk. the input is ?one-shotted? (50 k : pullup) sel_clk lvcmos input ?0' selects clk0, ?1' selects clk1 (50 k : pulldown) manual_override lvcmos input ?1' disables internal cloc k switch circuitry (50 k : pulldown) pll_en lvcmos input ?0' bypasses selected input reference around the phase-locked loop (50 k : pullup) mr lvcmos input ?0' resets the internal dividers forcing q outputs low. asynchronous to the clock (50 k : pullup) v cca power supply pll power supply v cc power supply digital power supply gnda power supply pll ground gnd power supply digital ground qa1 qa1 qa0 qa0 v cc v cc_pll man_override v cc inp0bad inp1bad clk_selected gnd ext_fb v cc qb0 qb0 qb1 qb1 qb2 qb2 v cc mr alarm_reset clk0 clk0 sel_clk clk1 clk1 gnd 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 mpc9993 pll_en ext_fb gnd
idt? intelligent dynamic clock switch (idcs) pll clock driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9993 3 mpc9993 intelligent dynamic clock switch (idcs) pll clock driver netcom advanced clock drivers device data freescale semiconductor 3 mpc9993 table 2. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those maximum values beyond which damage to t he device may occur. exposure to these conditions or conditions beyond thos e indicated may adversely affect device reli ability. functional operat ion at absolute-maxim um-rated conditions is not implied. symbol characteristics min max unit condition v cc supply voltage ?0.3 3.9 v v in dc input voltage ?0.3 v cc +0.3 v v out dc output voltage ?0.3 v cc +0.3 v i in dc input current r 20 ma i out dc output current r 50 ma t s storage temperature ?65 125 q c table 3. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc ? 2 v mm esd protection (machine model) 175 v hbm esd protection (human body model) 1500 v cdm esd protection (charged device model 1000 v lu latch-up immunity 100 ma c in input capacitance 4.0 pf inputs t ja thermal resistance junction to ambient jesd 51-3, single layer test board jesd 51-6, 2s2p multilayer test board 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 q c/w q c/w q c/w q c/w q c/w q c/w q c/w q c/w q c/w q c/w natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min t jc thermal resistance junction to case 23.0 26.3 q c/w mil-spec 883e method 1012.1 t j operating junction temperature (1) (continuous operation) mtbf = 9.1 years 1. operating junction temperature impacts device life time. maximum c ontinuous operating junction temperature should be selected according to the application life time requirement s (see application note an1545 for more inform ation). the device ac and dc parameters a re specified up to 110c junction temperature allowing the mpc9993 to be used in applications requiri ng industrial temperature ran ge. it is recommended that users of the mpc9993 employ thermal modeling analysis to assist in applying the j unction temperature specifica tions to their particular application. 110 q c
idt? intelligent dynamic clock switch (idcs) pll clock driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9993 4 mpc9993 intelligent dynamic clock switch (idcs) pll clock driver netcom advanced clock drivers device data 4 freescale semiconductor mpc9993 table 4. dc characteristics (v cc = 3.3 v 5%, t a = ? 40 to +85c) symbol characteristics min typ max unit condition lvcmos control inputs (mr , pll_en, sel_clk, man_override, alarm_reset ) v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage 0.8 v i in input current (1) 1. inputs have internal pull-up/pull-down re sistors affecting the input current. r 100 p a v in = v cc or gnd lvcmos control outputs (clk_selected, inp0bad, inp1bad) v oh output high voltage 2.0 v i oh = ?24 ma v ol output low voltage 0.55 v i ol = 24 ma lvpecl clock inputs (clk0, clk1, ext_fb) (2) 2. clock inputs driven by differ ential lvpecl compatible signals. v pp dc differential input voltage (3) 3. v pp is the minimum differential input voltage swi ng required to maintain ac characteristics. 0.1 1.3 v differential operation v cmr differential cross point voltage (4) 4. v cmr (dc) is the crosspoint of the differential input signal. func tional operation is obtained when the crosspoint is within the v cmr (dc) range and the input swing lies within the v pp (dc) specification. v cc ?1.8 v cc ?0.3 v differential operation i in input current (1) r 100 p a v in = v cc or gnd lvpecl clock outputs (qa[1:0], qb[2:0]) v oh output high voltage v cc ?1.20 v cc ?0.95 v cc ?0.70 v termination 50 : to v tt v ol output low voltage v cc ?1.90 v cc ?1.75 v cc ?1.45 v termination 50 : to v tt supply current i gnd maximum power supply current 180 ma gnd pins i cc_pll maximum pll supply current 15 ma v cc_pll pin
advanced clock drivers device data freescale semiconductor 5 mpc9993 table 5. ac characteristics (v cc = 3.3 v r 5%, t a = ?40 q c to +85 q c) (1) 1. ac characteristics apply for par allel output termination of 50 : to v cc ? 2 v. symbol characteristics min typ max unit condition f ref input reference frequency y 16 feedback 50 100 mhz pll locked f vco vco frequency range (2) y 16 feedback 2. the input reference frequency must match the vco lock range divided by the feedback divider ratio (fb): f ref = f vco y fb. 800 1600 mhz f max output frequency qa[1:0] qb[2:0] 50 100 100 200 mhz mhz pll locked f refdc reference input duty cycle 25 75 % t ( ? ) propagation delay spo, static phase offset (3) clk0, clk1 to any q 3. clk0, clk1 to ext_fb. -2.0 0.9 +2.0 1.8 ns ns pll_en=1 pll_en=0 v pp differential input voltage (4) (peak-to-peak) 4. v pp is the minimum differential input voltage swing required to maintain ac characteri stics including spo and device-to-device ske w. applicable to clk0, clk1 and ext_fb. 0.25 1.3 v v cmr differential input crosspoint voltage (5) 5. v cmr (ac) is the crosspoint of the differential input signal. norm al ac operation is obtained when the crosspoint is within the v cmr (ac) range and the input swing lies within the v pp (ac) specificatio n. violation of v cmr (ac) or v pp (ac) impacts the spo, device and part-to-part skew. applicable to clk0, clk1 and ext_fb. v cc -1.7 v cc -0.3 v t sk(o) output-to-output skew within qa[2:0] or qb[1:0] within device 50 80 ps ps ' per/cycle rate of change of period qa[1:0] (6) qb[2:0] (6) qa[1:0] (7) qb[2:0] (7) 6. specification holds for a cloc k switch between two input signals (clk0, clk1) no greater than 400 ps out of phase. delta peri od change per cycle is averaged over t he clock switch excursion. 7. specification holds for a clock switch between two i nput signals (clk0, clk1) at any phase difference (180 q ). delta period change per cycle is averaged over t he clock switch excursion. 20 10 200 100 50 25 400 200 ps ps ps ps dc output duty cycle 45 50 55 % t jit(cc) cycle-to-cycle jitter rms (1 v ) 47 ps t lock maximum pll lock time 10 ms t r , t f output rise/fall time 0.05 0.70 ns 20% to 80% idt? intelligent dynamic clock switch (idcs) pll clock driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9993 5 mpc9993 intelligent dynamic clock switch (idcs) pll clock driver netcom
idt? intelligent dynamic clock switch (idcs) pll clock driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9993 6 mpc9993 intelligent dynamic clock switch (idcs) pll clock driver netcom advanced clock drivers device data 6 freescale semiconductor mpc9993 applications information the mpc9993 is a dual clock pll with on-chip intelligent dynamic clock switch (idcs) circuitry. definitions primary clock: the input clk selected by sel_clk. secondary clock: the input clk not selected by sel_clk. pll reference signal: the clk selected as the pll reference signal by sel_clk or idcs. (idcs can override sel_clk). status functions clk_selected: clk_selected (l) indicates clk0 is selected as the pll reference signal. clk_selected (h) indicates clk1 is selected as the pll reference signal. inp_bad: latched (h) when it's clk is stuck (h) or (l) for at least one ext_fb period (pos to pos or neg to neg). cleared (l) on assertion of alarm_reset. control functions sel_clk: sel_clk (l) selects clk0 as the primary clock. sel_clk (h) selects clk1 as the primary clock. alarm_reset : asserted by a negativ e edge. generates a one-shot reset pulse that clears input_bad latches and clk_selected latch. pll_en: while (l), the pll reference signal is substituted for the vco output. mr : while (l), internal dividers are held in reset which holds all q outputs low. man override (h) (idcs is disabled, pll functions normally). pll reference signal (as indicated by clk_selected) will always be the clk selected by sel_clk. the status function inp_bad is active in man override (h) and (l). man override (l) (idcs is enabled, pll functions enhanced). the first clk to fail will latch it's inp_bad (h) status flag and select the other input as the clk_selected for the pll reference clock. once latched, the clk_selected and inp_bad remain latched until assertion of alarm_reset which clears all latches (inp_bads are cleared and clk_selected = sel_clk). note: if both clks are bad when alarm_reset is asserted, both inp_bads will be latched (h) after one ext_fb period and clk_selected will be latched (l) indicating clk0 is the pll reference signal. while neither inp_bad is latched (h), the clk_selected can be freel y changed with sel_clk. whenever a clk switch occurs, (manually or by idcs), following the next negative edg e of the newly selected pll reference signal, the next positive edge pair of ext_fb and the newly selected pll reference signal will slew to alignment. to calculate the overall uncertainty between the input clks and the outputs from multiple mpc9993's, the following procedure should be used. assumi ng that the input clks to all mpc9993's are exactly in phase, the total uncertainty will be the sum of the static phase offset, max i/o jitter, and output to output skew. during a dynamic switch, the output phase between two devices may be increased for a short period of time. if the two input clks are 400 ps out of ph ase, a dynamic switch of an mpc9993 will result in an instantaneous phase change of 400 ps to the pll reference signal without a corresponding change in the output phase (due to the limited response of the pll). as a result, the i/o phase of a device, undergoing this switch, will initially be 400 ps and diminish as the pll slews to its new phase alignment. this transient timing issue should be considered when analyzing the overall skew budget of a system. hot insertion and withdrawal in pecl applications, a powered up driver will experience a low impedance path through an mpc9993 input to its powered down vcc pins. in this case, a 100 ohm series resistance should be used in front of the input pins to limit the driver current. the resistor will have minimal impact on the rise and fall times of the input signals. acquiring frequency lock 1. while the mpc9993 is receiving a valid clk signal, assert man_override high. 2. the pll will phase and frequency lock within the specified lock time. 3. apply a high to low transition to alarm_reset to reset input bad flags. 4. de-assert man_override low to enable intelligent dynamic clock switch mode.
mpc9993 intelligent dynamic clock switch (idcs) pll clock driver netcom advanced clock drivers device data freescale semiconductor 7 mpc9993 package dimensions case 873a-04 issue c 32-lead lqfp package page 1 of 3 idt? intelligent dynamic clock switch (idcs) pll clock driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9993 7
idt? intelligent dynamic clock switch (idcs) pll clock driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9993 8 mpc9993 intelligent dynamic clock switch (idcs) pll clock driver netcom advanced clock drivers device data 8 freescale semiconductor mpc9993 package dimensions case 873a-04 issue c 32-lead lqfp package page 2 of 3
idt? intelligent dynamic clock switch (idcs) pll clock driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9993 9 mpc9993 intelligent dynamic clock switch (idcs) pll clock driver netcom advanced clock drivers device data freescale semiconductor 9 mpc9993 package dimensions page 3 of 3 case 873a-04 issue c 32-lead lqfp package
mpc9993 intelligent dynamic clock switch (idcs) pll clock driver netcom mpc9448 3.3 v/2.5 v lvcmos 1:12 clock fanout buffer netcom mc88915 low skew cmos pll clock drivers netcom mpc92459 900 mhz low voltage lvds clock synthesizer netcom ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future networks. contact: www.idt.com part numbers insert product name and document title netcom
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